In one promising application, researchers demonstrated the detection of specific odorous molecules with high resolution using a functionalized carbon nanotube based sensor. While the possibilities for CNT-based gas sensors are huge, the problem lies with the fabrication technologies, more specifically with a lack of technology for batch fabrication.

In order for CNT-based sensors to be able to compete with state-of-the-art CMOS (Complementary Metal Oxide Semiconductor) technology, researchers need to develop a low cost, reliable and large-scale reproducible CNT deposition process on the wafer level. Given the difficulties that they have encountered so far, scientists believe that a hybrid approach – to grow and integrate CNTs on CMOS wafers and use these CNTs to improve the performance of existing CMOS technology – could be a more realistic approach.

Researchers in the UK have presented a novel concept of wafer level localized growth of ‘spaghetti’-like CNTs on a fully processed CMOS substrate. This is the first successful proof of concept for growing CNTs at the post CMOS wafer stage. Reporting their findings in the online issue of Nanotechnology, a team from the Engineering Department at University of Cambridge and Cambridge CMOS Sensors Ltd used a standard silicon on insulator (SOI) CMOS process to fabricate the basic gas sensor (which incorporated a tungsten micro-heater and interdigitated electrodes) and on-chip circuitry from a commercial foundry.

The CNTs were grown locally and optimized on a wafer already containing CMOS circuits and devices. The researchers point out that “the integration of the two technologies – nanotechnology and conventional SOI CMOS – is of significant interest both from a device and application perspective. This is because CNTs are being used for the detection of different gases and vapours and SOI CMOS has the capability of low leakage current”.

To fabricate their gas sensor, the team used a SOI CMOS process from a commercial foundry. The SOI process handles 6 inch wafers with a 0.25 µm silicon active layer, and a 1.0 µm buried oxide layer. The device contains an embedded micro-heater and exposed interdigitated sensing electrodes. The interconnect metal (tungsten) of the high-temperature SOI process was used to form a resistive micro-heater. The use of tungsten metallization allows the device to operate at the potentially very high temperatures required for on-chip sensing material growth and gas sensor operation. The top layer of the devices is a passivated stable silicon nitride, which was etched away above the electrodes. The interdigitated sensing electrodes were formed from the top metal layer and are used to measure the change in resistance of the CNTs in the presence of a gas.

The dielectric membrane reduces the power consumption, for a given operating temperature (e.g. 500°C), while providing isolation from the electronic circuits present adjacent to the membrane. CNTs were grown onto interdigitated electrodes with tungsten micro-heater local growth at 725°C. This technique was extended to grow CNTs on more than one device to show the concept of wafer level growth by powering several micro-heaters simultaneously.

CNTs grown by this method were found through Raman spectroscopy to be practically identical and reproducible. Long term electrical resistance measurement was also carried out to check the stability of the CNTs, which is particularly useful for resistive chemical sensor applications.

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The research team that conducted the new investigation features physicists from the US National Institutes of Standards and Technology (NIST) and the Georgia Institute of Technology (Georgia Tech). The experts say that the moire patterns can also be used on multiple grids or atom arrays, not only on two. They add that using “atomic moire interferometry” can also help scientists determine the rotational orientation of the graphene sheets used in a variety of technological applications. Their work is published in the Physical Review B journal.

Given that one of the most complex areas of graphene research today is figuring out how the material changes its properties when stacked in multiple layers, being able to obtain a map of the strains that develop within it is extremely important. The electronic and transport properties of the single-atom-thick carbon compound can now be analyzed and determined with a much higher degree of accuracy than ever before, the NIST/Georgia Tech team says. Due to its revolutionary semiconducting properties, graphene is now hailed as the material of the future, at least in the electronics industry.

For the new experiments, Georgia Tech experts developed sheets of graphene on a silicon carbide substrate. After the samples were transferred at NIST, scientists here used a custom-built scanning tunnelling microscope (STM) to look at the graphene samples. The high resolve power on this instrument allows the experts to peer deep within the sample, past the topmost layer. It was through this method that the moire patterns became visible. Distinguishing them is fairly easy because of the hexagonal arrangement of carbon atoms in graphene. Any layers that are misplaced on top of others are immediately clear.

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Some of the greatest challenges of modern society are related to energy consumption, dissipation, and waste. Among these, present and future technologies based on nanoscale materials and devices hold great potential for improved energy conservation, conversion, or harvesting. A prominent example is that of integrated electronics, where power dissipation issues have recently become one of its greatest challenges. Power dissipation limits the performance of electronics from handheld devices (~10^–3 W) to massive data centres (~10⁹ W), all primarily based on silicon micro/nanotechnology.

Importantly, the figures for data centre energy consumption have doubled in five recent years, with waste heat requiring drastic cooling solutions. Such challenges are also evident at the individual micro-processor (CPU) level, where the race to increase operating frequency beyond a few GHz recently stopped when typical dissipated power reached 100 W/cm² (see figure below). Such electronic power and thermal challenges have negative impacts in areas from massive database servers to new applications like wearable devices, medical instrumentation, or portable electronics. In the latter situations, there is a basic trade-off between the available functionality and the need to carry heavy batteries to power it.

Despite tremendous progress over the past three decades, modern silicon transistors are still over three orders of magnitude (>1000×) more energy inefficient than fundamental physical limits. These limits have been estimated as approximately 3kBT ≈ 10^–20 J at room temperature for a binary switch with a single electron and energy level separation kBT, where kB is the Boltzmann constant and T is the absolute temperature. In the average modern microprocessor, the dissipated power is due, in approximately equal parts, to both leakage (or sleep) power and active (dynamic) switching power.

Power dissipation is compounded at the system level, where each CPU Watt demands approximately 1.5× more for the supply, PC board, and case cooling. Such power misuse is even more evident in systems built on otherwise power-efficient processors, e.g., in the case of the Intel Atom N270 (2.5 W power use) which is typically paired up with the Intel 945GSE chipset (11.8 W power use). At the other extreme, data centres require 50%–100% additional energy for cooling, which is now the most important factor limiting their performance, not the hardware itself.

Such energy challenges for the electronics infrastructure stem not only from the power supply side which calls for new energy sources, efficient batteries, or thermoelectrics, but also from the demand side, i.e., the need for more energy-efficient computing devices. Breakthroughs in our understanding and improvement of energy efficiency in nanoelectronics will have a global effect, impacting our energy supplies, budgets, and the environment.

On a broader scale, just over half the man-made energy in the world is wasted as heat (10¹³ W), from power plants and factories to car engines and the power bricks on our laptops. Efficiently reclaiming even a small percentage of such wasted heat would itself nearly satisfy the electricity needs of our planet. The fundamental issues at hand are, in fact, a two-sided problem: on one side, there is a significant need for low-energy computing devices, which is perhaps the biggest challenge in micro/nanoelectronics today. On the other side there is the challenge of waste heat dissipation, guiding, or conversion into useful electricity. On a large scale, a transistor twice as energy-efficient could lower power use by a significant percentage of the planet power budget. Such progress is crucial to maintaining progress in a post-CMOS world, and has great environmental implications as well.

Original article: Eric Pop, Energy Dissipation and Transport in Nanoscale Devices

Layers of h-BN a single atom thick have the same lattice structure as graphene, but electrically the materials are at opposite ends of the spectrum: h-BN is an insulator, whereas graphene, the single-atom-layer form of carbon, is highly conductive. The ability to assemble them into a single lattice could lead to a rich variety of 2-D structures with electric properties ranging from metallic conductor to semiconductor to insulator.

Because graphene is a conductor and h-BN is an insulator, the proportion of one to the other determines how well this new material conducts electrons. Lijie Ci and Li Song, both postdoctoral research scientists, found that by putting down domains of h-BN and carbon via chemical vapor deposition (CVD), they were able to control the ratio of materials in the film that resulted. The ratio of non-conductive boron nitride to highly conductive graphene determines the electrical properties of the new material.

Ci and Song are primary authors of a paper about the work that appeared in the online edition of Nature Materials. “From a graphene perspective, it now gives us an opportunity to explore band-gap engineering in two-dimensional layered systems,” Ajayan, their research director, said. The whole phase diagram of boron, carbon and nitrogen is fascinating, unexplored and offers a great playground for materials scientists.

“This is only the first instance showing that these structures can indeed be grown in 2-D like graphene,” Ajayan said. “I think the whole new field will be exciting for basic physics and electro-optical applications.” Graphene has been the subject of intense study in recent years for its high conductivity and the possibility of manipulating it on scales that go well below the theoretical limits for silicon circuitry. A layer of graphene is a hexagonal lattice of carbon atoms. In bulk, it’s called graphite, the stuff of pencil lead. Graphene was first isolated in 2004 by British scientists who used Scotch tape to pull single-atom layers from graphite.

“Graphene is a very hot material right now,” said Song, who had teamed with Ci to investigate doping graphene with various materials to determine its semiconducting properties. Knowing that both boron and nitrogen had already been used in doping bulk graphite, they decided to try cooking it via CVD onto a copper base. Structurally, h-BN is the same as graphene, a hexagon-shaped lattice of carbon atoms that looks like chicken wire. Ci and Song found that through CVD, graphene and h-BN merged into a single atomic sheet, with pools of h-BN breaking up the carbon matrix.

The critical factor for electronic materials is the band gap, which must be tuned in a controlled manner for applications. Graphene is a zero-gap material, but ways have been proposed to tailor this gap by patterning it into nanoscale strips and doping it with other elements. A one-atom-thick layer of a graphene and boron nitride hybrid is visible to the naked eye when deposited on a glass slide. Researchers are able to achieve fine control of the new material’s conductivity.

Ci and Song took a different approach through CVD, controlling the ratio of carbon to h-BN over a large, useful range. It remains challenging to produce single layers of the hybrid material, as most lab-grown films contain two or three layers. The researchers also cannot yet control the placement of h-BN pools in a single sheet or the rotational angles between layers – but they’re working on it.

In fact, having multiple layers of the hybrid at various angles creates even more possibilities, they said. “For pure graphene, this rotation will affect the electronic properties,” said Ci. The researchers are considering producing these materials on industrial-scale wafers. Graphene sheets several inches wide have already been synthesized in other labs, Ci said. And because graphene can be lithographically patterned and cut into shapes, the new material has great potential to be fabricated into useful devices with controllable electrical properties.

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